1. Field of the Invention
The present invention relates to semiconductor integrated circuits, and in particular to semiconductor integrated circuits which includes a circuit for generating a voltage higher than an externally supplied power supply voltage and a circuit for generating a negative voltage lower than a ground voltage.
2. Description of the Background Art
Present MOS semiconductor integrated circuits have boosted power supply circuit systems which generate an internal power supply voltage higher than an externally supplied power supply voltage and internally supply the same into the semiconductor integrated circuits so that high-level signals may be transmitted without lowering the level even if N-type MOSFETs are used.
Also, the MOS semiconductor integrated circuits have power supply circuit systems for generating an internal voltage lower than an externally supplied ground voltage and internally supply the same to the semiconductor integrated circuits so that a fast operation with a reduced power consumption may be achieved by reducing a coupling capacity at a drain node, and an operation margin may be increased by reducing a variation in threshold voltage due to a substrate effect.
The power supply circuit systems are required to detect a variation in the internal voltage due to an operation current and a leak current and thereby maintain the internal voltage within a range which can maintain the semiconductor integrated circuit at the normal state.
The variation in internal voltage is caused by flow of at least 2-digit number of currents including a current smaller than 100 nA caused by the semiconductor solid-state properties during standby and variation in performance due to manufacturing as well as a current on the order of 10 .mu.A caused by a circuit structure such as a bias current. When currents including up to an operation current on the order of 10 mA during the circuit operation are taken into consideration, the above variation in internal voltage is caused by flow of up to 5-digit number of currents.
FIG. 14 shows a structure of a boosted power supply circuit in the prior art having two detection levels. This circuit includes an output node N1, a first system circuit 1 provided for suppressing lowering from a set voltage and having a small current supply capacity per time, and a second system circuit 9 connected in parallel with first system circuit 1 and provided for rapid restoration from lowering from the set voltage.
First system circuit 1 includes a level detector 3 which has a detection level near the set voltage and has a response time t1 longer than a level detector 11, a ring oscillator 5 having a longer period T1 than a ring oscillator 13, and a charge pump 7 having a current supply capacity Q1 per period. In a continuous operation, the current supply capacity per time is equal to Q1/T1.
Second system circuit 9 includes level detector 11 which has a detection level at a voltage lower than the set voltage of level detector 3 and has a response time t2 shorter than level detector 3, a ring oscillator 13 having a shorter period T2 than ring oscillator 5, and a charge pump 15 of a current supply capacity Q2 per period. In the continuous operation, the current supply capacity per time is Q2/T2, and is larger than current supply capacity Q1/T1 of first system circuit.
FIG. 15 is a circuit diagram showing specific structures of ring oscillators 5 and 13. As shown in FIG. 15, ring oscillators 5 and 13 have the same circuit structure, and each include an NAND circuit 16 and inverters INV1-INV5 connected in series. However, MOS transistors forming inverters INV1-INV4 included in ring oscillator 5 have gate lengths sufficiently longer than those of MOS transistors of inverters INV1-INV4 included in ring oscillator 13. Also, period T1 of ring oscillator 5 is longer than period T2 of ring oscillator 13.
An operation of the boosted power supply circuit described above will now be described below.
Owing to electric charges Q accumulated in a decouple capacity Cd, the potential on output node N1 is maintained at a potential VPP (=Q/Cd):
During standby, charges Q accumulated in decouple capacitor Cd are lost due to a leak current which is unavoidable due to the semiconductor solid-state properties and a leak current which is unavoidable due to the circuit structures, so that potential VPP lowers. During operation, charges Q are lost and potential VPP lowers due to the operation current of circuits.
The leak current during standby in each semiconductor integrated circuit always exhibits substantially constant characteristics. However, the current during operation has such a feature that the current significantly varies depending on an operation pattern inside the semiconductor integrated circuit in contrast to the leak current during standby.
Therefore, the boosted power supply circuit having the two detection levels operates in such a manner that only first system circuit 1 having level detector 3 of response time t1 operates intermittently to maintain potential VPP on output node N1 and second system circuit 9 does not operate, when the operation or leak current is small and the charges which are lost per time are smaller than Q1/T1.
When the operation current or leak current further increases, the charges which are lost per time increase, so that current supply capacity Q1/T1 attained only by the continuous operation of the first system circuit 1 cannot maintain potential VPP set on output node N1, and therefore potential VPP lowers to the detection level of level detector 1.
When level detector 11 of response time t2 detects lowering of potential VPP on output node N1, ring oscillator 13 having a shorter period T2 than ring oscillator 5 will start the operation after elapsing of response time t2. In this manner, second system circuit 9 having current supply capacity Q2/T2 per time operates continuously for restoration from lowered potential VPP.
When potential VPP on output node N1 rises to the detection level of level detector 11 owing to the above continuous operation, the ring oscillator 13 will stop after elapsing of response time t2. However, at the time of this step, potential VPP is not yet completely restored.
The continuous operation of the first system circuit 1 is further required for completely restoring potential VPP to the set level.
In the above conventional boosted power supply circuit, second system circuit 9 is essentially required, for rapid restoring the lowered potential on output node N1, to detect lowering of potential VPP on output node N1 in a short response time t2 and operate charge pump 15 having large current supply capacity Q2/T2 per time with short period T2. It is not necessary to set current supply capacity Q2 per period to a large value.
If switching from the operation of second system circuit 9 to the operation of first system circuit 1 can be performed rapidly, potential VPP on output node N1 can be ultimately restored rapidly from the lowered state.
Although the foregoing description has been given on the boosted power supply circuit, the same is true with respect to a power supply circuit generating a negative voltage.